1. Field of the Invention
The present invention relates to active backplanes, and to the sealing of cells having active backplanes. It has special but not exclusive relevance to the assembly of light modulating cells comprising a light modulating material between the substrates.
2. Discussion of Prior Art
The device which is particularly described in this specification in connection with a preferred embodiment is a spatial light modulator in the form of a smectic liquid crystal layer disposed between an active semiconductor backplane and a common front electrode. It was developed in response to a requirement for a fast and, if possible, inexpensive, spatial light modulator comprising a relatively large number of pixels with potential application not only as a display device, but also for other forms of optical processing such as correlation and holographic switching. Our copending International Patent Applications of even filing and priority dates Applications (PCT/GB99/04285, U.S. Ser. No. 09/868,219, priority GB9827952.4; PCT/GB99/04286, U.S. Ser. No. 09/868,230, priority GB9827965.6; PCT/GB99/04282, U.S. Ser. Nos. 09/446,325 and 10/084,652, priority GB9827900.3; PCT/GB99/04279, U.S. Ser. No. 10/085,140, priority GB9827901.1; PCT/GB99/04274, U.S. Ser. Nos. 09/868,218 and 10/094,958, priority GB9827964.9; PCT/GB99/04275, U.S. Ser. No. 09/868,217, priority GB9827945.8; and PCT/GB99/04260 and PCT/GB99/04277, U.S. Ser. No. 09/868,241 and U.S. Ser. No. 09/868,242, both priority GB9827944.1) relate to other inventive aspects associated with the spatial light modulator.
During the course of development of the embodiment, a series of problems were encountered and dealt with, and the solutions to these problems (whether in the from of construction, function or method) are not necessarily restricted in application to the embodiment, but will find other uses. Thus not all of the aspects of the present invention are limited to liquid crystal devices, nor to spatial light modulators.
Nevertheless, it is useful to commence with a discussion of the problems encountered in developing the embodiment to be described later.
The liquid crystal phase has been recognised since the last century, and there were a few early attempts to utilise liquid crystal materials in light modulators, none of which gave rise to any significant successful commercial use. However, towards the end of the 1960""s and in the 1970""s, there was a renewed interest in the use of liquid crystal materials in light modulating, with increasing success as more materials, and purer materials became available, and as technology in general progressed.
Generally speaking, this latter period commenced with the use of nematic and cholesteric liquid crystal materials. Cholesteric liquid crystal materials found use as sensors, principally for measuring temperature or indicating a temperature change, but also for responding to, for example, the presence of impurities. In such cases, the pitch of the cholesteric helix is sensitive to the parameter to be sensed and correspondingly alters the wavelength at which there is selective reflection of one hand of circularly polarised light by the helix.
Attempts were also made to use cholesteric materials in electro-optic modulators, but during this period the main thrust of research in this area involved nematic materials. Initial devices used such effects as the nematic dynamic scattering effect, and increasingly sophisticated devices employing such properties as surface induced alignment, the effect on polarised light, and the co-orientation of elongate dye molecules or other elongate molecules/particles, came into being.
Some such devices used cells in which the nematic phase adopted a twisted (chiral) structure, either by suitably arranging surface alignments or by incorporating optically active materials in the liquid crystal phase. There is a sense in which such materials resemble cholesteric materials, which are often regarded as a special form of the nematic phase.
Initially, liquid crystal light modulators were in the form of a single cell comprising a layer of liquid crystal material sandwiched between opposed electrode bearing plates, at least one of the plates being transparent. The thickness of the liquid crystal layer in nematic cells is commonly around 20 to 100 microns.
At a later stage, electro-optic nematic devices comprising a plurality of pixels were being devised. Initially, these had the form of a common electrode on one side of a cell and a plurality of individually addressable passive electrodes on the other side of the cell (e.g. as in a seven-segment display), or, for higher numbers of pixels, intersecting passive electrode arrays on either side of the cell, for example row and column electrodes which were scanned. While the latter arrangements provided considerable versatility, there were problems associated with cross-talk between pixels.
The situation was exacerbated when analogue (grey scale) displays were required by analogue modulation of the applied voltage, since the optical response is non-linearly related to applied voltage. Addressing schemes became relatively complicated, particularly if dc balance was also required. Such considerations, in association with the relative slowness of switching of nematic cells, have made is difficult to provide real-time video images having a reasonable resolution.
Subsequently, active back-plane devices were produced. These comprise a back plane comprising a plurality of active elements, such as transistors, for energising corresponding pixels. Two common forms are thin film transistor on silica/glass backplanes, and semiconductor backplanes. The active elements can be arranged to exercise some form of memory function, in which case addressing of the active element can be accelerated compared to the time needed to address and switch the pixel, easing the problem of displaying at video frame rates.
Active backplanes are commonly provided in an arrangement very similar to a dynamic random access memory (DRAM) or a static random access memory (SRAM). At each one of a distributed array of addressable locations, a SRAM type active backplane comprises a memory cell including at least two coupled transistors arranged to have two stable states, so that the cell (and therefore the associated liquid crystal pixel) remains in the last switched state until a later addressing step alters its state. Each location electrically drives its associated liquid crystal pixel, and is bistable per se, i.e. without the pixel capacitance. Power to drive the pixel to maintain the existing switched state is obtained from busbars which also supply the array of SRAM locations. Addressing is normally performed from peripheral logic via orthogonal sets (for example column and row) addressing lines.
In a DRAM type active backplane, a single active element (transistor) is provided at each location, and forms, together with the capacitance of the associated liquid crystal pixel, a charge storage cell. Thus in this case, and unlike a SRAM backplane, the liquid crystal pixels are an integral part of the DRAM of the backplane. There is no bistability associated with the location unless the liquid crystal pixel itself is bistable, and this is not the case so far as nematic pixels are concerned. Instead, reliance is placed on the active element providing a high impedance when it is not being addressed to prevent leakage of charge from the capacitance, and on periodic refreshing of the DRAM location.
Thin film transistor (TFT) backplanes comprise an array of thin film transistors distributed on a substrate (commonly transparent) over what can be a considerable area, with peripheral logic circuits for addressing the transistors, thereby facilitating the provision of large area pixellated devices which can be directly viewed. Nevertheless, there are problems associated with the yields of the backplanes during manufacture, and the length of the addressing conductors has a slowing effect on the scanning. When provided on a transparent substrate, such as of glass, TFT arrays can actually be located on the front or rear surface of a liquid crystal display device.
In view of their overall size, the area of the TFT array occupied by the transistors, associated conductors and other electrical elements, e.g. capacitors is relatively insignificant. There is therefore no significant disadvantage in employing the SRAM configuration as opposed to the DRAM configuration. This sort of backplane thus overcomes many of the problems associated with slow switching times of liquid crystal pixels.
Generally, the active elements in TFT backplanes are diffusion transistors and the like as opposed to FETS, so that the associated impedances are relatively low and associated charge leakage relatively high in the xe2x80x9cOFFxe2x80x9d state.
Semiconductor active backplanes are limited in size to the size of semiconductor substrate available, and are not suited for direct viewing with no intervening optics. Nevertheless their very smallness aids speed of addressing of the active elements. This type of backplane commonly comprises FETs, for example MOSFETs or CMOS circuitry, with associated relatively high impedances and relatively low associated charge leakage in the xe2x80x9cOFFxe2x80x9d state.
However, the smallness also means that the area of the overall light modulation (array) area occupied by the transistors, associated conductors and other electrical elements, e.g. capacitors can be relatively significant, particularly in the SRAM type which requires many more elements than the DRAM type. Being opaque to visible light, a semiconductor backplane would provide the rear substrate of a light modulator or display device.
At a later period still, substantial development occurred in the use of smectic liquid crystals. These have potential advantages over nematic phases insofar as their switching speed is markedly greater, and with appropriate surface stabilisation the ferroelectric smectic C phases should provide devices having two stable alignment states, i.e. a memory function.
The thickness of the layer of liquid crystal material in such devices is commonly much smaller than in the corresponding nematic devices, normally being of the order of a few microns at most. In addition to altering the potential switching speed, this increases the unit capacitance of a pixel, easing the function of a DRAM active backplane in retaining a switched state at a pixel until the next address occurs.
However, as the thickness of the liquid crystal approaches the dimensions associated with the underlying structure of the backplane and/or the magnitude of any possible deformation of the liquid crystal cell structure by flexing or other movenent of the substrates, problems arise, for example as to the uniformity of response across the pixel and the capability for short circuiting across the cell thickness. The alignment in chiral smectic liquid crystal cells is also frequently very sensitive to mechanical factors, and can be destroyed by mechanical impulses or shock.
Sealing of the Cell As indicated above, an active backplane comprises a display or light modulation area in which are distributed a plurality of locations each comprising at least one active element, together with peripheral logic for addressing the locations. Essentially, the only necessary connections between the logic and the locations are by addressing busbars such as column and row conductors, and, for SRAMS, power supply lines.
Externally, connections need to be made to the peripheral logic for data supply lines, power lines etc., and for this purpose an edge portion, or more likely at east two neighboring or opposed edge portions, of the active backplane is/are left projecting beyond the overlying transparent front electrode substrate.
It is necessary to seal a liquid crystal cell peripherally, for example with adhesive. In the case of a cell having an active semiconductor backplane, the two substrates are small, and it is not uncommon to find cells where the adhesive overlies at least a part of the peripheral logic and/or the edge of the area bearing the addressable locations, indicative of the difficulty which can be experienced in accurately locating the upper substrate relative to the lower substrate and controlling the flow of the adhesive. Thus there can be relatively little control over the exact location of the adhesive material in at least some instances.
Our copending application PCT/GB99/04286 (U.S. Ser. No. 09/868,230) relates to a method of assembling and sealing a first substrate to a second substrate in spaced opposed relation, the method comprising the steps of:
(a) providing a glue plate having an aperture having a shape corresponding to that of the first substrate but being of marginally smaller dimensions;
(b) covering the glue plate with adhesive;
(c) accurately bringing the first substrate into register with the aperture of the glue plate so that the peripheral region only of the first substrate is coated with adhesive; and
(d) removing the first substrate from the plate and bringing it accurately into a desired register with the second substrate.
Preferably, at least one of the first and second substrates comprises electrical elements such as one or more conductors, or other passive or active electrical elements. Preferably at least one of the first and second substrates is transparent or translucent.
While the substrates may have identical areas, and be brought into complete register, the method covers instances where at least one edge of the second substrate projects beyond the first substrate, for example to facilitate electrical connection thereto.
In the device more particularly described hereafter, the second substrate is an active backplane, and the first (top) substrate provides a transparent counterelectrode and only extends as far as is necessary to seal the liquid crystal portion of the device, i.e. as defined by the array and a peripheral glue lane to be described later. All four peripheral regions of the backplane may project and thus be suitable for carrying pads for external electrical connections. Other circuitry of the backplane occupies these peripheral regions and so is also not covered or overlapped by the top substrate.
The top substrate is, transparent and carries on its underside a transparent electrode layer. A metal electrode, for example of aluminium, but more preferably copper, silver or gold, for connecting the transparent electrode layer to the backplane or elsewhere is formed on a side surface of the top substrate (e.g. by evaporating or sputtering), and extends around the corner to overlie and connect to the transparent electrode.
In a preferred form of the method, there is provided a jig having first and second cooperating portions for accurately locating the first and second substrates when they are brought into register during step (d).
In one form of the method, steps (a) to (c) comprise the step of positioning the first substrate on the first jig portion and the glue plate on the second jig portion so that the first substrate and the aperture of the glue plate can be brought accurately into the required register. Step (d) comprises replacing the glue plate on the second jig portion by the second substrate, and bringing the first and second substrates into the required register.
However, more preferably, the jig comprises a third portion functioning as or similarly to the second portion, steps (a) to (c) include the steps of positioning the first substrate on the first jig portion and the apertured plate on the third jig portion, so that the first substrate and the aperture can be brought accurately into the required register, and step (d) comprises placing the second substrate on the second jig portion for bringing the first and second substrates into the required register.
As particularly described below, the jig portions and the apertured glue plate may be arranged to permit assembly of a plurality of cells simultaneously. The first and second jig portions may respectively comprise first and second plates for mounting the first and second substrates at predetermined positions, together with locating means (for example including pins extending through holes in the plates) for ensuring that the first and second plates can be brought together in a desired relationship. Where provided, the third jig portion is similarly constructed, its plate being the glue plate. Where the third jig portion is not provided, the glue plate will be similarly located on locating means of the second jig portion.
Preferably, the adhesive is a UV setting adhesive. Although spacer elements may be provided within the glue bead itself, for example glass beads of a predetermined narrow size distribution, it is preferred to use glue without such elements and to rely on spacers already on place on one or both substrates. The provision of such spacers forms the subject of our copending application PCT/GB99/04282, U.S. Ser. No. 09/446,325.
Preferably, where the substrates comprise an active backplane and a transparent electrode, the first substrate is the transparent electrode. In such a case, it is preferred that the backplane projects beyond the transparent electrode on at least one side to facilitate electrical connections thereto.
Preferably the method is applied to the production of liquid crystal cells, and includes the step of inserting or placing liquid crystal material between the substrates. This can be performed prior to step (a), between steps (a) and (b), or after step (b). The last option is particularly suited to and/or preferred for the production of smectic liquid crystal cells and/or liquid crystal cells incorporating an active backplane.
Although spacing of the cell substrates within the area of the cell can be effected by including individual spacer elements distributed within the liquid crystal or other material within the cell itself, it is preferred to provide spacers located on, and distributed over, one or both substrates, as discussed in more detail in our copending application PCT/GB99/04282, U.S. Ser. No. 09/446,325.
While the assembly method is paticularly suited to constructions having semiconductor active backplanes, in view of the difficulty in accurately handling and locating them because of their size, other cell-like devices can be similarly assembled, including liquid crystal cells with TFT backplanes, other liquid crystal cells and other light modulators and displays.
Glue Lanes In much of the prior art it appears that little consideration has been given to the effect that a sealant between cell substrates may have on the operation or life of a cell, particularly where the sealant comes into contact with the active elements of the cell, whether the electronic components of the cell or its contents, for example liquid crystal material, as mentioned previously. Such contact may occur through inaccurate initial placement of the adhesive, misalignment of the substrates to be scaled, or by the sealant being squeezed during tile seating process.
European Patent Application No. 93916162.6 discloses a liquid crystal display device in which conductors which run between an array and external control circuitry, all on the same substrate are locally thickened to provide a spacing effect. Although there is no particular reference to the desirability of keeping the adhesive away from critical cell components, the showing in the figures would appear to indicate that in this particular case there is ample room in the conductor region to place an adhesive without any of the foregoing problems occurring, However, the device is described in terms of a thin film transistor array, and these are most commonly used in large scale display devices where there is plenty of room on the underlying substrate to provide for easy accommodation of an adhesive strip away from both the array and the control circuitry.
U.S. Pat. No. 5,644,373 (Furushima) also discloses a TFT device with an annular space between addressing circuitry and an array of TFTs; however, in this case the annular space is described merely as xe2x80x9ca separating regionxe2x80x9d and is shown as being filled from side to side with adhesive, which thus contact both the array and the addressing circuitry.
By contrast, pat of the problem in scaling cells with active semiconductor backplanes resides in the closeness of the array of addressable locations to the peripheral logic, due to the smallness of the semiconductor area and the need to utilise it efficiently. In such a context, it is belied that there has been no previous recognition of the problems arising from contact between adhesive or sealant and critical cell components, and that the provision of a sufficiently broad dedicated xe2x80x9cglue lanexe2x80x9d for accommodating the sealant has not previously been disclosed or even suggested. By providing more space, it is possible to locate the peripheral glue strip essentially only over the addressing lines, or addressing and power lines, coupling the more densely occupied peripheral logic regions to the more densely occupied array region.
Reducing the amount of contact between the glue and functioning elements of the backplane is advantageous because the glue, or spacer elements distributed within the glue to space the substrates, can comprise electrically conductive impurities which will produce and electrical short across part of the cell or active backplane (the term xe2x80x9cconductivexe2x80x9d needs to be construed in context, insofar for example, the resistance of an FET in an active backplane is extremely high, and so needs only slight conductivity to be effectively shorted out).
The present invention provides semiconductor backplane comprising spaced first and second regions, an array of electronic or electrical elements in said first region, logic elements for addressing said array in said second region, and conductors coupling said first and second regions, characterized in that the first and second regions are sufficiently widely spaced to permit the presence of an adhesive sealing strip therebetween without substantial contact with the first and second regions. In practice, the minimum useful width of adhesive that can be applied is around 300 microns, so that allowing for tolerances in relative positioning, the width of the glue lane should be at least 500 microns, more preferably at least 1000 micons, and even more preferably 1500 microns.